Design and Implementation of Flexible Arbiter for DDR SDRAM Memory Controller to Support 9 Arbitration Schemes on FPGA

As fabrication technology continues to improve, smaller feature sizes allow increasingly more integration of system components onto a single die. Communication between these Components can become the limiting factor for performance unless careful attention is given to designing high performance Arbiter. Amongst various components on the device, a high-performance arbiter has to be design which decides the bus grant signal to component. In this Project, we propose the design and implementation of a flexible arbiter for the DDR SDRAM Memory Controller to support three priority policies: 1) fixed priority, 2) round robin, and 3) dynamic priority and three data multiplexing modes 1) transfer, 2) transaction, and 3) desired transfer length. In total, there are nine possible arbitration schemes. The proposed arbiter, which is self-motivated (SM), selects one of the nine possible arbitration schemes based upon the priority-level notifications and the desired transfer length from the masters so that arbitration leads to the maximum performance. Along with the design of memory controller to provide proper commands For SDRAM initialization, read/write accesses and memory refresh. DDR SDRAM uses double data rate architecture to achieve high-speed data transfers. DDR SDRAM (referred to as DDR) transfers data on both the rising and falling edge of the clock. This DDR controller is typically implemented in a system between the DDR and the Processor units.